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INTEGRATED CIRCUITS
DATA SHEET
UDA1321 Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
Preliminary specification Supersedes data of 1998 May 12 File under Integrated Circuits, IC01 1998 Oct 06
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
UDA1321
FEATURES General * Universal Serial Bus (USB) stereo Digital-to-Analog Converter (DAC) system with adaptive (5 to 55 kHz) 20-bits digital-to-analog conversion and filtering * USB-compliant audio and Human Interface Device (HID) * Supports 12 Mbits/s full-speed serial data transmission * Supports multiple audio data formats (8, 16 and 24 bits) * Supports headphone and line output * Fully automatic `Plug-and-Play' operation * High linearity * Wide dynamic range * Superior signal-to-noise ratio (typical 95 dB) * Low total harmonic distortion (typical 90 dB) * 3.3 V power supply * Efficient power management * Low power consumption * On-chip master clock oscillator, only an external crystal is required * Partly programmable USB descriptors and configuration via I2C-bus. Sound processing * Separate digital volume control for left and right channel * Soft mute * Digital bass and treble tone control * External Digital Sound Processor (DSP) option possible via standard I2S-bus or Japanese digital I/O format * Selectable clipping prevention * Selectable Dynamic Bass Boost (DBB) * On-chip digital de-emphasis.
Document references * "USB Specification" * "USB Common Class Specification" * "USB Device Class Definition for Audio Devices" * "Device Class Definition for Human Interface Devices (HID)" * "USB HID Usage Table". APPLICATIONS * USB monitors * USB speakers * USB headsets * USB telephone/answering machines * USB links in consumer audio devices. GENERAL DESCRIPTION The UDA1321 is a stereo CMOS digital-to-analog bitstream converter designed for USB-compliant audio playback devices and multimedia audio applications.The UDA1321 is an adaptive asynchronous sink USB audio device with a continuous sampling frequency (fs) range from 5 to 55 kHz. It contains a USB interface, an embedded microcontroller and an Asynchronous Digital-to-Analog Converter (ADAC). The USB interface is the interface between the USB, the ADAC and the microcontroller. The USB interface consists of an analog front-end and a USB processor. The analog front-end transforms the differential USB data to a digital data stream. The USB processor buffers the input and output data from the analog front-end and handles all low-level USB protocols. The USB processor selects the relevant data from the universal serial bus, performs an extensive error detection and separates control information (input and output) and audio information (input only).
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
The control information becomes accessible at the microcontroller. The audio information becomes available at the digital I/O output or is fed directly to the ADAC. The microcontroller handles the high-level USB protocols, translates the incoming control requests and manages the user interface via General Purpose (GP) pins and an I2C-bus. The ADAC enables the wide and continuous range of input sampling frequencies. By means of a Sample Frequency Generator (SFG), the ADAC is able to reconstruct the average sample frequency from the incoming audio samples. The ADAC also performs the sound processing.
UDA1321
The ADAC consists of FIFO registers, a unique audio feature processing DSP, the SFG, digital up-sampling filters, a variable hold register, a Noise Shaper (NS) and a Filter Stream DAC (FSDAC) with integrated filter and line output drivers. The audio information is applied to the ADAC via the USB processor or via the digital I/O input. An external DSP can be used for adding extra sound processing features via the digital I/O-bus. The UDA1321 supports the standard I2S-bus data input format and the LSB-justified serial data input format with word lengths of 16, 18 and 20 bits. The wide dynamic range of the bitstream conversion technique used in the UDA1321 guarantees a high audio sound quality.
QUICK REFERENCE DATA SYMBOL Supplies VDD IDD(tot) IDD(ps) supply voltage total supply current supply current in power-save mode total harmonic distortion-plus-noise to signal ratio note 1 note 3 3.0 - - 3.3 50 18 3.6 - - V mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Dynamic performance DAC THD + N ---------------------S fs = 44.1 kHz; RL = 5 k at input signal of 1 kHz (0 dB) - - at input signal of 1 kHz (-60 dB) - - 90 - -90(2) -80 0.0032 0.01 -30(2) -20 3.2 95 0.66 10 - - dB % dB % dBA V
S/Nbz Vo(FS)(rms)
signal-to-noise ratio at bipolar zero full-scale output voltage (RMS value) audio sample input frequency operating ambient temperature
A-weighted at code 0000H VDD = 3.3 V
General characteristics fi(sample) Tamb Notes 1. VDD is the supply voltage on pins VDDA, VDDE, VDDI and VDDX. VSS is the ground on pins VSSA, VSSE, VSSI and VSSX. All VDD and VSS pins must be connected to the same supply or ground respectively. 2. The audio information from the USB interface is fed directly to the ADAC. 3. The power-save mode (power management) is not supported in the UDA1321/N101; see Chapter "USB-DAC UDA1321/N101 (Firmware sw 2.1.1.7)". 5 0 - 25 55 70 kHz C
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UDA1321H/N101 UDA1321T/N101 UDA1321PS/N101 QFP64 SO28 SDIP32 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm plastic small outline package; 28 leads; body width 7.5 mm plastic shrink dual in-line package; 32 leads (400 mil)
UDA1321
VERSION SOT319-2 SOT136-1 SOT232-1
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
BLOCK DIAGRAM
handbook, full pagewidth
UDA1321
D+
D-
TC RTCB SHTCB TEST CONTROL BLOCK ANALOG FRONT-END SCL SDA EA USB-PROCESSOR PSEN ALE P2.0 GP4/BCKO GP3/WSO GP2/DO GP1/DI GP0/BCKI GP5/WSI MICROCONTROLLER DIGITAL I/O P2.4 P2.5 P2.6 P2.7 P0.0 FIFO REGISTERS fs SAMPLE FREQUENCY GENERATOR AUDIO FEATURE PROCESSING DSP fs UP-SAMPLE FILTERS 64fs VSSX XTAL1 XTAL2 VDDX OSC TIMING 128fs 3rd-ORDER NOISE SHAPER VARIABLE HOLD REGISTER VDDE VSSE VSSI VDDI VDDO VSSO VDDA VSSA LEFT DAC RIGHT DAC P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.1 P2.2 P2.3
UDA1321H UDA1321T UDA1321PS
VOUTL
VOUTR
REFERENCE VOLTAGE
Vref
MGM839
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
PINNING SYMBOL GP5/WSI SCL SDA P0.7 EA GP1/DI PSEN ALE GP2/DO P2.0 P2.1 GP3/WSO GP4/BCKO SHTCB D- P2.2 P2.3 D+ P2.4 P2.5 P2.6 P2.7 VDDI VSSI VSSE VDDE VSSX XTAL1 XTAL2 VDDX Vref VSSA VDDA VOUTR VSSO 1998 Oct 06 PIN QFP64 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 29 30 32 36 37 38 39 42 44 45 46 49 PIN SDIP32 29 30 31 n.a. n.a. 32 n.a. n.a. 1 n.a. n.a. 2 3 4 6 n.a. n.a. 7 n.a. n.a. n.a. n.a. 8 9 10 11 13 14 15 16 18 19 20 21 22 PIN SO28 25 26 27 n.a. n.a. 28 n.a. n.a. 1 n.a. n.a. 2 3 4 5 n.a. n.a. 6 n.a. n.a. n.a. n.a. 7 8 9 10 11 12 13 14 15 16 17 18 19 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O - - - - - I O - O - - O - 6 DESCRIPTION
UDA1321
general purpose pin 5 or word select input serial clock input (I2C-bus) serial data input/output (I2C-bus) Port 0.7 of the microcontroller external access (active LOW) general purpose pin 1 or data input program store enable (active LOW) address latch enable (active HIGH) general purpose pin 2 or data output for extra DSP chip Port 2.0 of the microcontroller Port 2.1 of the microcontroller general purpose pin 3 or master word select output for extra DSP chip general purpose pin 4 or master bit clock output for extra DSP chip shift clock TCB input (active HIGH) negative data line of the differential data bus conform to the USB-standard Port 2.2 of the microcontroller Port 2.3 of the microcontroller positive data line of the differential data bus conform to the USB-standard Port 2.4 of the microcontroller Port 2.5 of the microcontroller Port 2.6 of the microcontroller Port 2.7 of the microcontroller digital supply voltage core digital ground core digital ground I/O pins digital supply voltage I/O pins crystal oscillator ground crystal oscillator input 1 crystal oscillator output 2 crystal oscillator supply voltage reference output voltage analog ground analog supply voltage right channel output voltage operational amplifier ground
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
SYMBOL VDDO VOUTL TC P0.0 P0.1 P0.2 P0.3 P0.4 RTCB P0.5 P0.6 GP0/BCKI n.c. PIN QFP64 51 53 55 56 57 58 59 60 61 62 63 64 1, 16, 26, 27, 28, 31, 33, 34, 35, 40, 41, 43, 47, 48, 50, 52, 54 PIN SDIP32 23 24 25 n.a. n.a. n.a. n.a. n.a. 26 n.a. n.a. 27 5, 12, 17, 28 PIN SO28 20 21 22 n.a. n.a. n.a. n.a. n.a. 23 n.a. n.a. 24 n.a. I/O - O I I/O I/O I/O I/O I/O I I/O I/O I/O - DESCRIPTION operational amplifier supply voltage left channel output voltage test control input (active HIGH) Port 0.0 of the microcontroller Port 0.1 of the microcontroller Port 0.2 of the microcontroller Port 0.3 of the microcontroller Port 0.4 of the microcontroller
UDA1321
asynchronous reset input for test control box (active HIGH) Port 0.5 of the microcontroller Port 0.6 of the microcontroller general purpose pin 0 or master bit clock input not connected
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
UDA1321
handbook, full pagewidth
64 GP0/BCKI
53 VOUTL
61 RTCB
57 P0.1
56 P0.0
63 P0.6
62 P0.5
58 P0.2
60 P0.4
59 P0.3
52 n.c. 51 VDDO 50 n.c. 49 VSSO 48 n.c. 47 n.c. 46 VOUTR 45 VDDA 44 VSSA 43 n.c. 42 VREF 41 n.c. 40 n.c. 39 VDDX 38 XTAL2 37 XTAL1 36 VSSX 35 n.c. 34 n.c. 33 n.c. VDDE 32
n.c. 1 GP5/WSI 2 SCL SDA 3 4
P0.7 5 EA 6 GP1/DI 7 PSEN 8 ALE 9 GP2/DO 10 P2.0 11 P2.1 12 GP3/WSO 13 GP4/BCKO 14 SHTCB 15 n.c. 16 D- 17 P2.2 18 P2.3 19 D+ 20 P2.4 21 P2.5 22 P2.6 23 P2.7 24 VDDI 25 n.c. 26 n.c. 27 n.c. 28 VSSI 29 VSSE 30 n.c. 31
UDA1321H
54 n.c.
55 TC
MGM850
Fig.2 Pin configuration QFP64.
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Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
UDA1321
handbook, halfpage
handbook, halfpage
GP2/DO 1 GP3/WSO 2 GP4/BCKO 3 SHTCB 4 D- 5 D+ 6 VDDI 7 VSSI 8 VSSE 9 VDDE 10 VSSX 11 XTAL1 12 XTAL2 13 VDDX 14
MGM840
28 GP1/DI 27 SDA 26 SCL 25 GP5/WSI 24 GP0/BCKI 23 RTCB 22 TC
GP2/DO 1 GP3/WSO 2 GP4/BCKO 3 SHTCB 4 n.c. 5 D- 6 D+ 7 VDDI 8
32 GP1/DI 31 SDA 30 SCL 29 GP5/WSI 28 n.c. 27 GP0/BCKI 26 RTCB 25 TC
UDA1321T
21 VOUTL 20 VDDO 19 VSSO 18 VOUTR 17 VDDA 16 VSSA 15 Vref
UDA1321PS
VSSI 9 VSSE 10 VDDE 11 n.c. 12 VSSX 13 XTAL1 14 XTAL2 15 VDDX 16
MGM841
24 VOUTL 23 VDDO 22 VSSO 21 VOUTR 20 VDDA 19 VSSA 18 Vref 17 n.c.
Fig.3 Pin configuration SO28.
Fig.4 Pin configuration SDIP32.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
FUNCTIONAL DESCRIPTION All bold-faced parameters given in this data sheet such as `bAlternateSetting' are part of the USB specification as described in "USB Device Class Definition for Audio Devices". The Universal Serial Bus (USB) Data and power are transferred via the USB by a 4-wire cable. The signalling occurs via two wires and point-to-point segments. The signals on each segment are differentially driven into a cable of 90 intrinsic impedance. The differential receiver features input sensitivity of at least 200 mV and sufficient common mode rejection. The analog front-end The analog front-end is an on-chip generic USB transceiver. It is designed to allow voltage levels up to VDD from standard or programmable logic to interface with the physical layer of the USB. It is capable of receiving and transmitting serial data at full speed (12 Mbits/s). The USB processor The USB processor forms the interface between the analog front-end, the ADAC and the microcontroller. The USB processor consists of: * The Philips Serial Interface Engine (PSIE) * The Memory Management Unit (MMU) * The Audio Sample Redistribution (ASR) module. THE PHILIPS SERIAL INTERFACE ENGINE AND MEMORY MANAGEMENT UNIT (PSIE AND MMU) The PSIE and MMU translate the electrical USB signals into bytes and signals. Depending upon the USB device address and the USB endpoint address, the USB data is directed to the correct endpoint buffer on the PSIE and MMU interface. The data transfer could be of the bulk, isochronous, control or interrupt type. The USB device address is configured during the enumeration process. The UDA1321 has three endpoints. These are: * Control endpoint 0 * Status interrupt endpoint * Isochronous data sink endpoint. The amount of bytes per packet on the control endpoint is limited by the PSIE and MMU hardware to 8 bytes per packet.
UDA1321
The PSIE is the digital front-end of the USB processor.This module recovers the 12 MHz USB clock, detects the USB sync word and handles all low-level USB protocols and error checking. The MMU is the digital back-end of the USB processor. It handles the temporary data storage of all USB packets that are received or sent over the bus. Three types of packets are defined on the USB. These are: * Token packets * Data packets * Handshake packets. The token packet contains information about the destination of the data packet. The audio data is transferred via an isochronous data sink endpoint and consequently no handshaking mechanism is used. The MMU also generates a 1 kHz clock that is locked to the USB Start-Of-Frame (SOF) token. THE AUDIO SAMPLE REDISTRIBUTION (ASR) MODULE The ASR module reads the audio samples from the MMU and distributes these samples equidistant over a 1 ms frame period. The distributed audio samples are translated by the digital I/O module to standard I2S-bus format or Japanese digital I/O format. The ASR module generates the bit clock and the word select signal of the digital I/O. The digital I/O formats the received audio samples to one of the four specified serial digital audio formats (standard I2S-bus, 16, 18 or 20 bits LSB-justified). The microcontroller The microcontroller receives the control information selected from the USB by the USB processor. It handles the high-level USB protocols and the user interfaces. The major task of the software process, that is mapped upon the microcontroller, is to control the different modules of the UDA1321 in such a way that it behaves as a USB device. Therefore the microcontroller: * Interprets the USB requests and maps them upon the UDA1321 application * Controls the internal operation of the UDA1321 and the digital I/O pins * Communicates with the external world (EEPROM) using the I2C-bus facility and the general purpose I/O pins.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
The Asynchronous Digital-to-Analog Converter (ADAC) The ADAC receives USB audio information from the USB processor or from the digital I/O-bus. The ADAC is able to reconstruct the sample clock from the rate at which the audio samples arrive and handles the audio sound processing. After processing, the audio signal is up-sampled, noise-shaped and converted to analog output voltages capable of driving a line output. The ADAC consists of: * A Sample Frequency Generator (SFG) * First-In First-Out (FIFO) registers * An audio feature processing DSP * Two digital up-sample filters * A variable hold register * A digital Noise Shaper (NS) * A Filter Stream DAC (FSDAC) with integrated filter and line output drivers. THE SAMPLE FREQUENCY GENERATOR (SFG) The SFG controls the timing signals for the asynchronous digital-to-analog conversion. By means of a digital PLL, the SFG automatically recovers the applied sampling frequency and generates the accurate timing signals for the audio feature processing DSP and the up-sample filters. FIRST-IN FIRST-OUT (FIFO) REGISTERS The FIFO registers are used to store the audio samples temporarily coming from the USB processor or from the digital I/O input. The use of a FIFO register (in conjunction with the SFG) is necessary to remove all jitter present on the incoming audio signal. THE AUDIO FEATURE PROCESSING DSP A DSP processes the sound features. The control and mapping of the sound features is explained in Section "Controlling the USB Digital-to-Analog Converter (DAC)". Depending on the sampling rate (fs) the DSP has four frequency domains in which the treble and bass are regulated (see Table 1). The domain is chosen automatically. THE UP-SAMPLE FILTERS AND VARIABLE HOLD REGISTER After the audio feature processing DSP two up-sample filters and a variable hold register increase the oversampling rate to 128fs. Table 1
UDA1321
Frequency domains for audio processing SAMPLE FREQUENCY (kHz) 5 to 12 12 to 25 25 to 40 40 to 55
DOMAIN 1 2 3 4 THE NOISE SHAPER
A 3rd-order noise shaper converts the oversampled data to a noise-shaped bitstream for the FSDAC. The in-band quantization noise is shifted to frequencies well above the audio band. THE FILTER STREAM DAC (FSDAC) The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed because of the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. USB Digital-to-Analog Converter (DAC) descriptors In a typical USB environment the USB host has to know which kind of devices are connected. For this purpose each device contains a number of USB descriptors. These descriptors describe, from different points of view (USB configuration, USB interface and USB endpoint), the capabilities of a device. Each of them can be requested by the host. The collection of descriptors is denoted as a descriptor map. This descriptor map will be reported to the USB host during enumeration and on request. The full descriptor map is implemented in the firmware exploiting the full functionality of the UDA1321. The USB descriptors and their most important fields, in relationship to the characteristics of the UDA1321 are briefly explained below. GENERAL DESCRIPTORS The UDA1321 supports one configuration containing a control interface, an audio interface and a HID interface. The descriptor map that describes this configuration is partly fixed and partly programmable.
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Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
UDA1321
handbook, full pagewidth
INPUT TERMINAL
FEATURE UNIT
FU
OUTPUT TERMINAL
IT
OT
MBK530
Fig.5 Audio function topology.
The programmable part can be retrieved from one of four configuration maps located in the firmware or from an I2C-bus EEPROM. At start-up one of four configuration maps can be selected depending on the logical combination of GP3 and GP0. It is possible to overwrite this configuration map with a configuration map loaded from an I2C-bus EEPROM. AUDIO DEVICE CLASS SPECIFIC DESCRIPTORS The audio device class is partly specified with standard descriptors and partly with specific audio device class descriptors. The standard descriptors specify the number and the type of the interface or endpoint. The UDA1321 supports 7 different audio modes: * 8-bit Pulse Code Modulation (PCM) mono or stereo audio data * 16-bit PCM mono or stereo audio data * 24-bit PCM mono or stereo audio data * Zero bandwidth mode. Each mode is defined as an alternate setting of the audio interface, selectable with the standard audio streaming interface descriptor bAlternateSetting field. The seven alternate settings are described in more detail by the specific audio device class descriptors. The UDA1321 supports the Input Terminal (IT), Output Terminal (OT) and the Feature Unit (FU) descriptors. The input and output terminals are not controllable via the USB. The feature unit provides the basic manipulation of the incoming logical channels. The supported sound features are: * Volume control * Mute control * Treble control * Bass control * Bass boost control. 1998 Oct 06 12
Table 2
Audio bandwidth at each audio mode wMaxPacketSize 56 (88 x 1 x 56) 112 (88 x 2 x 56) 112 (168 x 1 x 56) 224 (168 x 2 x 56) 168 (248 x 1 x 56) 336 (248 x 2 x 56)
AUDIO MODE 8-bit PCM; mono 8-bit PCM; stereo 16-bit PCM; mono 16-bit PCM; stereo 24-bit PCM; mono 24-bit PCM; stereo
The maximum number of audio data samples within a USB packet arriving on the isochronous sink endpoint is restricted by the buffer capacity of this isochronous endpoint. The maximum buffer capacity is 336 bytes/ms. For each alternate setting with audio, a maximum bandwidth is claimed as indicated in the standard isochronous audio data endpoint descriptor wMaxPacketSize field. To allow a small overshoot in the number of audio samples per packet, the top sample frequency of 55 kHz is taken in the calculation of the bandwidth for each alternate setting. For each alternate setting, with its own isochronous audio data endpoint descriptor, wMaxPacketSize field is then defined as described in Table 2. Although in a specific UDA1321 application no endpoint control properties can be used upon the isochronous adaptive sink endpoint, the descriptors are still necessary to inform the host about the definition of this endpoint: isochronous, adaptive, sink, continuous sampling frequency (at input side of this endpoint) with lower bound of 5 kHz and upper bound of 55 kHz. The audio class specific descriptors can be requested with the `Get descriptor: configuration request', which returns all the descriptors, except the device descriptor. HUMAN INTERFACE DEVICE SPECIFIC DESCRIPTORS The inputs defined on the UDA1321 are transmitted via the USB to the host according to the HID class. The host
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
responds with the appropriate settings via the audio device class for the audio related parts or via the HID class for the HID related inputs and outputs of the UDA1321. A HID descriptor is necessary to inform the host about the conception of the user interface. The host communicates via the HID device driver using either the control pipe or the interrupt pipe. The UDA1321 uses USB endpoint 0 (control pipe) to respond to the HID specific `Get/set report request' to receive or transmit data from or to the UDA1321. The UDA1321 uses the status interrupt endpoint as interrupt pipe for polling asynchronous data. The UDA1321 is a high-speed device. The maximum transaction size is 64 bytes per USB frame and the polling rate is defined at a maximum of every 1 ms. The host requests the configuration descriptor which includes the standard interface descriptor, the HID endpoint descriptor and the HID descriptor. The HID device driver of the host then requests the report descriptor. Report descriptors are composed of pieces of information about the device. Each piece of information is called an item. All items have a 1-byte prefix that contains the item tag, type and size. In the UDA1321 only the short item basic type is used. The hosts HID device driver will parse the report descriptor and the defined items. By examining all of these items, the HID class driver is able to determine the size and composition of data reports from the device. The main items of the UDA1321 are input and output reports. Input reports are sent via the interrupt pipe (UDA1321 USB address 3). Input and output reports can be requested by the host via the control endpoint (USB address 0). The UDA1321 supports a maximum of three pushbuttons, which represents a certain feature of the UDA1321. If pressed by the user the pushbutton will go to its `ON' state, if not pressed the pushbutton will go back to its `OFF' state. The UDA1321 supports a maximum of two outputs for e.g. user LEDs. For more information about the input and output functions of the UDA1321 see the application documentation of the device.
UDA1321
Controlling the USB Digital-to-Analog Converter (DAC) This section describes the functionality of the feature unit of the UDA1321. The mapping of this functionality onto USB descriptors is as implemented in the firmware. The sound features as defined in the "USB Device Class Definition for Audio Devices" are mapped on the UDA1321 specific feature registers by the microcontroller. These specific sound features are: * Volume control (separate for left and right stereo channels, no master channel) * Mute control (only master channel) * Treble control (only master channel) * Bass control (only master channel) * Dynamic bass boost control (only master channel). These specific features can be activated via the host (audio device class requests) or via the GP pins (HID plus audio device class requests). Via the I2C-bus the user is able to download the necessary configuration data for different applications (definition of the function of the GP pins, with or without digital I/O functionality, etc.). The mapping and control of the standard USB audio features and UDA1321 specific features is described below. VOLUME CONTROL Volume control is possible via the host or via predefined GP pins. The setting of 0 dB is always referenced to the maximum available volume setting. Table 3 gives the mapping of wVolume value (as defined in the "USB Device Class Definition for Audio Devices") upon the actual volume setting of the USB DAC. When using the UDA1321, the range is 0 down to -60 dB (in steps of 1 dB) and - dB. Independant control of `left'/'right' volume is possible. It should be noted that wVolume bits B7 to B0 are not used. Values above 0 dB are returned as 0 dB. The volume value at start-up of the device is defined in the selected configuration map. Balance control is possible via the separate volume control option of both channels. Therefore the characteristics of the balance control are equal to the volume control characteristics.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
Table 3 Volume control characteristics; note 1 wVOLUME B15 0 1 1 1 1 1 1 1 1 1 1 ... 1 1 1 1 ... 1 Note B14 0 1 1 1 1 1 1 1 1 1 1 ... 1 1 1 1 ... 0 B13 0 1 1 1 1 1 1 1 1 1 1 ... 0 0 0 0 ... 0 B12 0 1 1 1 1 1 1 1 1 1 1 ... 0 0 0 0 ... 0 B11 0 1 1 1 1 1 1 1 1 0 0 ... 0 0 0 0 ... 0 B10 0 1 1 1 1 0 0 0 0 1 1 ... 1 1 0 0 ... 0 B9 0 1 1 0 0 1 1 0 0 1 1 ... 0 0 1 1 ... 0 B8 0 1 0 1 0 1 0 1 0 1 0 ... 1 0 1 0 ... 0 VOLUME USB SIDE (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 ... -59 -60 -61 -62 ... -
UDA1321
VOLUME USB DAC (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 ... -59 -60 - - ... -
1. The volume control characteristics of this table are in accordance with the latest Audio Device Class Definition. The volume control characteristics of the UDA1321/N101 are slightly different; see Chapter "USB-DAC UDA1321/N101 (Firmware sw 2.1.1.7)" MUTE CONTROL Mute is one of the sound features as defined in the "USB Device Class Definition for Audio Devices". The mute control request data bMute controls the position of the mute switch. The position can be either on or off. When bMute is true the feature unit is muted. When bMute is false the feature unit is not muted. When the mute is active for the master channel, the value of the sample is decreased smoothly to zero following a raised cosine curve. There are 32 coefficients used to step down the value of the data, each one being used 32 times before stepping to the next. This amounts to a mute transition of 23 ms at fs = 44.1 kHz. When the mute is released, the samples are returned to the full level again following a raised cosine curve with the same coefficients being used in reversed order. The mute, on the master channel is synchronized to the sample clock, so that operation always takes place on complete samples. A mute can be given via the host or by pressing a predefined GP pin.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
TREBLE CONTROL
UDA1321
The treble control is available for the master channel of the UDA1321. Treble can be regulated in three modes: minimum, flat and maximum mode. The preferred mode is selected at start-up of the device (configuration map). The corner frequency is 3000 Hz for the minimum mode and 1500 Hz for the maximum mode. The treble range is from 0 to 6 dB in steps of 2 dB. It should be noted that the negative treble values as defined in the "USB Device Class Definition for Audio Devices" are not supported by the UDA1321; the 0 dB value is returned as 0 dB. Table 4 gives the mapping of the bTreble value upon the actual treble setting of the USB DAC. Table 4 Treble control characteristics; note 1 bTREBLE B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1. The 2 dB step is not supported in the UDA1321/N101; see Chapter "USB-DAC UDA1321/N101 (Firmware sw 2.1.1.7)". B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 TREBLE USB SIDE (dB) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 ... 5.25 ... 7.25 ... 9.25 ... 31.75 6 0 6 6 0 6 6 0 6 6 0 6 4 0 4 2 0 2 TREBLE USB DAC (dB) minimum 0 flat 0 maximum 0
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
BASS CONTROL
UDA1321
The bass control is available for the master channel of the UDA1321. Bass can be regulated in three modes: minimum, flat and maximum mode. The preferred mode is selected at start-up of the device (configuration map). The Bass range is from 0 to about 14 dB (minimum mode) or about 24 dB (maximum mode) in steps of 2 dB. It should be noted that the negative bass values as defined in the "USB Device Class Definition for Audio Devices" are not supported by the UDA1321; the 0 dB value is returned as 0 dB. The maximum Bass value which will be reported to the host is always 24 dB independent of the mode. The maximum mode is the most accurate mode when the Bass values are reported to the host. The corner frequency is 100 Hz for the minimum mode and 75 Hz for the maximum mode. Table 5 gives the mapping of the bBass value upon the actual bass setting of the USB DAC. Table 5 Bass control characteristics bBASS B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 1 0 1 0 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 BASS USB SIDE (dB) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 ... 5.25 ... 7.25 ... 9.25 ... 11.25 ... 13.25 ... 15.25 ... 17.25 ... 13.7 0 17.3 11.9 0 15.2 10.2 0 13.3 8.4 0 11.3 6.8 0 9.4 5.2 0 7.4 3.7 0 5.4 2.4 0 3.6 1.1 0 1.7 BASS USB DAC (dB) minimum 0 flat 0 maximum 0
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
bBASS B7 0 0 0 0 0 0 0 0 B6 1 0 1 1 1 1 1 1 B5 0 1 0 1 1 1 1 1 B4 0 1 1 0 0 1 1 1 B3 1 1 0 0 1 0 1 1 B2 1 0 1 1 1 1 1 1 B1 0 1 0 0 0 0 0 1 B0 1 1 1 1 1 1 1 1 BASS USB SIDE (dB) 19.25 ... 21.25 ... 23.25 ... 25.25 ... 27.25 ... 29.25 ... 31.25 ... 31.75 13.7 0 13.7 0 13.7 0 13.7 0 13.7 0 13.7 0 13.7 0
UDA1321
BASS USB DAC (dB) minimum 13.7 flat 0 maximum 19.2 21.2 23.2 23.2 23.2 23.2 23.2 23.2
DYNAMIC BASS BOOST CONTROL Bass boost is one of the sound features as defined in the "USB Device Class Definition for Audio Devices". The bass boost control request data bBassBoost controls the position of the bass boost switch. The position can be either on or off. When bBassBoost is true the bass boost is activated. When bBassBoost is false the bass boost is off. When clipping prevention is active, the bass is reduced to avoid clipping with high volume settings. Bass boost is selectable via the configuration map (see Table 6). If byte 19H is loaded with 00H, bass boost is not reported to the USB host by the device.
Clipping prevention If the maximum of the bass plus volume gives clipping, the Bass is reduced. Clipping prevention is selectable via the configuration map. De-emphasis De-emphasis is one of the properties which is not supported by the USB. De-emphasis for 44.1 kHz can be predefined in the configuration map selected at start-up of the UDA1321.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
UDA1321
handbook, full pagewidth
3.3 V
3.3 V 22 k
3.3 V 22 k
3.3 V 22 k GP0 GP3
TR3 KEY 1 SW1 1.5 k 22 k KEY 2 SW2 1 1 D2 22 k TR1 TR2 22 k 1 2 3 4 6 10 nF 10 nF 22 pF 22 pF 22
MGM109
Vbus D1
2
22 k GP5
2
USB-B connector 5 Vbus
22
D- D+
Fig.6 Diode matrix selection.
Start-up and configuration of the UDA1321 START-UP OF THE UDA1321 After power-on, an internal power-on reset signal becomes HIGH after a certain RC-time (R = 5 k and C = Cref). During 10 ms after power-on reset the UDA1321 has to initiate the internal settings. After the power-on reset the UDA1321 becomes master of the I2C-bus. The UDA1321 tries to read the eventually connected EEPROM and if an EEPROM is detected, the internal descriptors are overwritten and the selected port configuration is applied. If no EEPROM is detected, the UDA1321 tries to read the logical levels of GP3 and GP0. A choice can be made from four configuration maps via these two pins. CONFIGURATION SELECTION OF THE UDA1321 VIA A DIODE
MATRIX
After selecting a configuration map the user cannot change the chosen settings for the GP pins, internal configuration, descriptors, etc. For more information about the four (vendor specific) configuration maps and the diode matrix see the application documentation. CONFIGURATION OPTIONS OF THE UDA1321 VIA AN I2C-BUS EEPROM If an EEPROM is detected (reading byte 0 as AAH and byte 1 as 55H), the UDA1321 will use the configuration map in the EEPROM instead of one of four configuration maps. The layout of the configuration map is fixed, the values (except bytes 0 and 1) are user definable (see Table 6). If the user wants to change these values (the manufacturers name for instance), this can be achieved via the EEPROM code. The communication between the UDA1321 and the external I2C-bus device is based on the standard I2C-bus protocol given in the Philips specification "The I2C-bus and how to use it (including specifications)", which can be ordered using the code 9398 393 40011. The I2C-bus has two lines: a clock line SCL and a serial data line SDA (see Fig.7).
The UDA1321 uses a configuration map to hold a number of specific configurable data on hardware, product, component and USB configuration level. At start-up without EEPROM, the UDA1321 will scan the logical levels of GP3 and GP0. With these two pins it is possible to select one of the four possible (vendor specific) configuration maps. This selection can be achieved via a diode matrix (see Fig.6).
1998 Oct 06
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SDA t BUF t LOW tr tf t HD;STA t SP
handbook, full pagewidth
Philips Semiconductors
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
19
SCL
t HD;STA P S
t HD;DAT
t HIGH
t SU;DAT
t SU;STA
t SU;STO Sr
MBC611
P
Preliminary specification
UDA1321
Fig.7 Definition of timing of the I2C-bus.
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
Table 6 BYTE (HEX) 0 1 2 - - ASR control register Control options for the UDA1321 via the EEPROM configuration map; note 1 REGISTER NAME COMMENTS recognition pattern; do not change it recognition pattern; do not change it robust word clock serial I2S-bus output format 7 6 and 5 BIT AAH 55H 0 = off 1 = on
UDA1321
VALUE
00 = I2S-bus 01 = 16-bit LSB 10 = 18-bit LSB 11 = 20-bit LSB 0 = mono phase inversion off 1 = mono phase inversion on 00 = reserved 01 = 8-bit audio 10 = 16-bit audio 11 = 24-bit audio 0 = mono 1 = stereo 0 = stop 1 = go 0 00 = flat 01 = minimum 10 = minimum 11 = maximum 0 = de-emphasis off 1 = de-emphasis on 0 = L L, R R 1 = L R, R L 0 = asynchronous 1 = synchronous 0 = no mute 1 = mute active 0 = no reset ADAC 1 = reset ADAC
phase inversion bits per sample modi
4 3 and 2
audio mode ASR register start-up mode 3 ADAC mode register 0 selection ADAC mode register audio feature mode
1 0 7 6 and 5
de-emphasis channel manipulation synchronous/asynchronous control mute control reset ADAC
4 3 2 1 0
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
BYTE (HEX) 4 REGISTER NAME ADAC mode register 1 COMMENTS selection ADAC mode register digital PLL lock speed BIT 7 6 and 5 1
UDA1321
VALUE
00 = lock after 512 samples 01 = lock after 2048 samples 10 = lock after 4096 samples 11 = lock after 16384 samples 0 = adaptive 1 = fixed 00 = adaptive 01 = fixed state 1 10 = fixed state 2 11 = fixed state 3 00 = I2S-bus 01 = 16-bit LSB 10 = 18-bit LSB 11 = 20-bit LSB 0 = clipping prevention off 1 = clipping prevention on 0 = no I2S-bus used 1 = I2S-bus used only if I2S-bus is used; 0 = 4 pins I2S-bus 1 = 6 pins I2S-bus 0 = function 1 1 = function 2 (see Tables 7, 8 and 9)
digital PLL lock mode digital PLL mode
4 3 and 2
serial I2S-bus input format
1 and 0
5
I/O selection register
clipping I2S-bus usage 4/6 pins I2S-bus (see Section "The general purpose pins (GP0 to GP5)") GP4 GP3 GP2 GP1 GP0
7 6 5
4 3 2 1 0
6 7 8 9 A B C D E F 10
GP0 Usage Page if HID selected GP0 Usage if HID selected reserved reserved GP3 Usage Page if HID selected GP3 Usage if HID selected reserved reserved GP4 Usage Page if HID selected GP4 Usage if HID selected reserved
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
BYTE (HEX) 11 REGISTER NAME GP1 and GP2 outputs definition register reserved reserved application GP2 function 2 COMMENTS BIT 7 6 5
UDA1321
VALUE
0 = HID output 2 1 = LED output 2 (activated when DBB is active) 0 = HID output 1 1 = LED output 1 (activated when mute is active) normal or inversed output functionality: 0 = according Table 7 1 = inversed
application GP1 function 2
4
polarity GP2 function 1 polarity GP1 function 1 polarity GP2 function 2 polarity GP1 function 2 12 13 14 15 16 GP1 Usage Page if HID selected GP1 Usage if HID selected GP2 Usage Page if HID selected GP2 Usage if HID selected time between releasing standby and enabling the audio output; steps of 20 ms time between `no isochronous data present' and activating the mute output; steps of 1 s (only applicable for function 1, no digital I/O communication) time between activating the mute output and activating the standby output; steps of 5 s (only applicable for function 1, no digital I/O communication); when filled-in with zero, standby will not be activated default bass boost value on top of Bass USB DAC for Dynamic Bass Boost (DBB); see Table 5
3 2 1 0
17
18
19
bass boost = register value; if bass boost + Bass USB DAC is larger then the maximum value of Table 5, the maximum value is used (no bass boost in flat mode) volume = -register value
1A 1B 1C 1D 1E 1F 20
default volume value of USB DAC idVendor high byte idVendor low byte idProduct high byte idProduct low byte bmAttributes maximum power steps of 2 mA with maximum 500 mA 22
1998 Oct 06
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
BYTE (HEX) 21 22 23 24 25 26 27 28 32 36 46 54 Notes - - - pointer language string pointer manufacturer string pointer product string pointer serial number language string manufacturer string product string serial number; note 2 32 36 46 54 REGISTER NAME COMMENTS wTerminalType high byte wTerminalType low byte BIT
UDA1321
VALUE
1. An extensive description of the USB control options is available in the "USB Device Class Definition for Audio Devices". 2. The serial number is only supported in the external configuration map and not in the four internal configuration maps. The general purpose pins (GP0 to GP5) The UDA1321 has 6 General Purpose (GP) pins; these are pins GP0 to GP5. These can be used either for digital I/O functions or for general purposes. The configurations presented are as implemented in the standard firmware. There are basically three port configurations: * No digital I/O communication * 4-pins digital I/O communication * 6-pins digital I/O communication. These port configurations can be selected via the configuration map at start-up of the UDA1321. The user can make a selection between two functions for each of the pins GP0 to GP4 (see byte 5 in Table 6), except if digital I/O communication is selected (see Tables 7, 8 and 9).
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
Table 7 PIN GP5 GP4 GP3 GP0 GP2 GP1 Notes 1. The input pins must have a pull-up resistor. 2. Connect/disconnect: holds the USB `disconnected' as long as the initialization is not finished. outputs; programmable No digital I/O communication INPUT/OUTPUT output; not programmable; note 2 inputs; programmable; note 1 FUNCTION 1 connect/disconnect alarm mute; note 3 HID input 2 HID input 1 standby; note 4 mute; note 5
UDA1321
FUNCTION 2 connect/disconnect HID input 3 HID input 2 HID input 1 HID/LED output 2; note 6 HID/LED output 1; note 6
3. Alarm mute: input to switch the sound off; specially used if the USB host program does not respond to the control.This pin acts directly on the sound and passes the mute to the USB host. 4. Standby is switched on (output becomes LOW) after a programmable time if mute is active (see Byte 18 of Table 6). 5. Mute is switched on (output becomes LOW) after a programmable time if the isochronous data flow is interrupted (see Byte 17 of Table 6). 6. For selection between HID/LED application see configuration map byte 11 (output is active HIGH). Table 8 PIN GP5 GP4 GP3 GP2 GP1 GP0 Notes 1. Connect/disconnect: holds the USB `disconnected' as long as the initialization is not finished. 2. Alarm mute: input to switch the sound off; specially used if the USB host program does not respond to the control. This pin acts directly on the sound and passes the mute to the USB host. input; programmable 4-pins digital I/O communication INPUT/OUTPUT output; not programmable; note 1 digital I/O-bus BCKO WSO DO DI HID input 1 FUNCTION 1 connect/disconnect BCKO WSO DO DI alarm mute; note 2 FUNCTION 2 connect/disconnect
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
Table 9 PIN GP5 GP4 GP3 GP2 GP1 GP0 Filter characteristics 6-pins digital I/O communication INPUT/OUTPUT digital I/O-bus WSI BCKO WSO DO DI BCKI FUNCTION
UDA1321
The overall filter characteristic of the UDA1321 in flat mode is given in Fig.8. The overall filter characteristic of the UDA1321 includes the filter characteristics of the DSP in flat mode plus the filter characteristic of the FSDAC (fs = 44.1 kHz). DSP extension port An external DSP can be used for adding extra sound processing features via the digital I/O-bus. The UDA1321 supports the standard I2S-bus data protocol and the LSB-justified serial data input format with word lengths of 16, 18 and 20 bits. Using the 4-pins digital I/O-bus the UDA1321 device acts as a master, controlling the BCK and WS signals. The period of the WS signal is determined by the number of samples in the 1 ms frame of the USB. This implies that the WS signal does not have a constant period time, but is jittery. Using the 6-pins digital I/O-bus GP2, GP3 and GP4 are the output pins (master) and GP0, GP1 and GP5 are the input pins (slave). For characteristic timing of the I2S-bus input interface see Figs 9 and 10.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
UDA1321
handbook, full pagewidth
-0
MGM110
-20 volume (dB) -40
-60
-80
-100
-120
-140
-160 0 10 20 30 40 50 60 70 80 f (kHz) 90 100
Fig.8 Overall filter characteristics of the UDA1321.
handbook, full pagewidth
LEFT
WS
RIGHT th;WS ts;WS
tr BCK
tBCK(H)
tf
tBCK(L)
Tcy
ts;DAT th;DAT
DATA
LSB
MSB
MGK003
Fig.9 Timing of digital I/O input signals.
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WS 1 BCK DATA MSB B2 LSB MSB B2 INPUT FORMAT I2S-BUS LSB MSB 2 LEFT 3 >=8 1 2 RIGHT 3 >=8 WS LEFT 16 BCK DATA MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS MSB B2 B15 LSB 15 2 1
Philips Semiconductors
handbook, full pagewidth
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
RIGHT 16 15 2 1
27
WS LEFT 18 BCK DATA MSB B2 B3 B4 17 16 15 WS 20 BCK 19 LEFT 18 17 16 15 DATA MSB B2 B3 B4 B5 B6
RIGHT 2 1 18 17 16 15 2 1
B17
LSB
MSB
B2
B3
B4
B17
LSB
LSB-JUSTIFIED FORMAT 18 BITS
RIGHT 2 1 20 19 18 17 16 15 2 1
Preliminary specification
B19
LSB
MSB
B2
B3
B4
B5
B6
B19
LSB
MGK002
UDA1321
LSB-JUSTIFIED FORMAT 20 BITS
Fig.10 Input formats.
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL All digital I/Os VI/O IO Tj Tstg Tamb Ves DC input/output voltage range output current -0.5 - - - - - 25 - - PARAMETER CONDITIONS MIN. TYP.
UDA1321
MAX.
UNIT
VDD 4
V mA C C C
Temperature junction temperature storage temperature operating ambient temperature 0 -55 0 -3000 -300 125 +150 70
Electrostatic handling electrostatic handling note 1 note 2 Notes 1. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 2. Equivalent to discharging a 200 pF capacitor through a 2.5 H series inductor and a 25 resistor. For pin VDDO the electrostatic handling is limited to 250 V. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) QFP64 SDIP32 SO28 PARAMETER thermal resistance from junction to ambient CONDITIONS in free air 48 57 65 K/W K/W K/W VALUE UNIT +3000 +300 V V
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
RECOMMENDED OPERATING CONDITIONS SYMBOL VDD VI VI/O supply voltage DC input voltage for D+ and D- DC input voltage for the digital I/Os PARAMETER MIN. 3.0 0.0 0.0 - - TYP. 3.3
UDA1321
MAX. 3.6 VDD VDD V V V
UNIT
DC CHARACTERISTICS VDD = 3.3 V; VSS = 0 V; Tamb = 25 C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified. SYMBOL Supplies VDDE VDDI VDDA VDDO VDDX IDDE IDDI IDDA IDDO IDDX Ptot Ptot(ps) digital supply voltage I/O pins digital supply voltage core analog supply voltage operational amplifier supply voltage crystal oscillator supply voltage digital supply current I/O pins digital supply current core analog supply current operational amplifier supply current crystal oscillator supply current total power dissipation total power dissipation in power-save mode static DC input voltage static DC output voltage HIGH static DC output voltage LOW high impedance state data line output leakage current differential input sensitivity differential common mode voltage single-ended receiver threshold voltage transceiver input capacitance LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage input leakage current input capacitance pin to ground 3.0 3.0 3.0 3.0 3.0 - - - - - - - 3.3 3.3 3.3 3.3 3.3 3 36 4.2 4.0 2.1 165 60 3.6 3.6 3.6 3.6 3.6 - - - - 15.0(2) - - V V V V V mA mA mA mA mA mW mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
note 1
note 3
Inputs/outputs D+ and D- VI VOH VOL ILO VI(dif) VCM(dif) VSE(RX)th CI(TRX) VIL VIH VOL VOH ILI Ci -0.5 RL = 15 k to ground 2.8 RL = 1.5 k to 3.6 V - - 0.2 0.8 0.8 pin to ground - - 0.7VDDI - - - - - - - - - - VDDI VDDI 0.3 10 - 2.5 2.0 20 0.3VDDI VDDI 0.4 - 1 5 V V V A V V V pF V V V V A pF
Digital inputs/outputs
- - VDDI - 0.4 - - - - -
1998 Oct 06
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
SYMBOL Filter stream DAC Vref Vo(cm) Ro Ro(L) Co(L) Notes reference voltage common mode output voltage output resistance at pins VOUTL and VOUTR output load resistance output load capacitance - - - 2.0 - 0.5VDDA - 0.5VDDA - 11 - - - - 50 PARAMETER CONDITIONS MIN. TYP.
UDA1321
MAX.
UNIT
V V k pF
1. This value depends strongly on the application. The specified value is the typical value obtained using the application as given in Fig.12. 2. At start-up of the oscillator. 3. The power-save mode (power management) is not supported in the UDA1321/N101; see Chapter "USB-DAC UDA1321/N101 (Firmware sw 2.1.1.7)".
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
AC CHARACTERISTICS VDD = 3.3 V; VSS = 0 V; Tamb = 25 C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - - - - - - 12.00 1.0000 0.0 0.0 - - 0.0 0.0 - - TYP.
UDA1321
MAX.
UNIT
Driver characteristics D+ and D- (full-speed mode) tr tf trf(m) Vcr R(o)driver fi(sample) ffs(D) tfr tJ1(dif) tJ2(dif) tW(EOP) tEOP(dif) tJR1 tJR2 tEOPR1 tEOPR2 rise time fall time matching rise/fall time (tr/tf) output signal crossover voltage driver output resistance steady-state drive CL = 50 pF CL = 50 pF 4 4 90 1.3 28 20 20 110 2.0 43 ns ns % V
Data source timings D+ and D- (full-speed mode) audio sample input frequency full-speed data rate frame interval source differential jitter to next transition source differential jitter for paired transitions source End Of Packet (EOP) width differential to EOP transition skew receiver data jitter tolerance to next transition receiver data jitter tolerance for paired transitions EOP width at receiver must reject as EOP EOP width at receiver must accept as EOP 5 11.97 0.9995 -3.5 -4.0 160 -2.0 -18.5 -9.0 40 82 55 12.03 1.0005 +3.5 +4.0 175 +5.0 +18.5 +9.0 - - kHz Mbits/s ms ns ns ns ns ns ns ns ns
Serial input/output data timing; see Fig.9 fclk(sys) fi(WS) tr tf tBCK(H) tBCK(L) ts;DAT th;DAT ts;WS th;WS system clock frequency word select input frequency rise time fall time bit clock HIGH time bit clock LOW time data set-up time data hold time word select set-up time word select hold time - 5 - - 55 55 10 20 20 10 12 - - - - - - - - - - 55 20 20 - - - - - - MHz kHz ns ns ns ns ns ns ns ns
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
SYMBOL PARAMETER CONDITIONS MIN. TYP.
UDA1321
MAX.
UNIT
SDA and SCL lines (standard I2C-bus); see Fig.7 fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tSU;STO tHD;DAT tSU;DAT tr tf CL(bus) fosc gm Ro Ci(XTAL1) Ci(XTAL2) Istart tsu(POR) RES Vo(FS)(rms) SVRR Vo ct SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition SCL LOW time SCL HIGH time set-up time for a repeated START condition set-up time for a STOP condition data hold time data set-up time rise time of both SDA and SCL signals fall time of both SDA and SCL signals load capacitance for each bus line 0 4.7 4.0 4.7 4.0 4.7 4.0 5.0 250 - - - - - 13.5 450 10 4.5 4.3 - - - - - - - - - - - - 100 - - - - - - 0.9 - 1000 300 400 - - 30.5 1450 12 5.5 15.0 - - - - - - kHz s s s s s s s ns ns ns pF
Oscillator; note 1 oscillator frequency duty factor transconductance output resistance parasitic input capacitance at XTAL1 parasitic input capacitance at XTAL2 start current 48 50 23.0 700 11 5.0 8.8 - - 0.66 60 0.03 95 MHz % mS pF pF mA
Power-on reset power-on reset set-up time notes 2 and 3 5Cref 16 VDD = 3.3 V fripple = 1 kHz; Vripple(p-p) = 0.1 V maximum volume RL = 5 k - - - - ms
Filter Stream DAC (FSDAC) resolution full-scale output voltage (RMS value) supply voltage ripple rejection of VDDA and VDDO channel unbalance crosstalk between channels bits V dB dB dB
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
SYMBOL PARAMETER CONDITIONS fs = 44.1 kHz; RL = 5 k at input signal of 1 kHz (0 dB) at input signal of 1 kHz (-60 dB) S/Nbz Notes signal-to-noise ratio at bipolar zero A-weighted at code 0000H - - - - 90 -90(4) 0.0032 -30(4) 3.2 95 MIN. TYP.
UDA1321
MAX.
UNIT
(THD + N)/S total harmonic distortion-plus-noise to signal ratio
-80 0.01 -20 10 -
dB % dB % dBA
1. A 3rd overtone crystal of 48 MHz must be used in combination with a filter connected to the oscillator output (XTAL2), (L = 1.5 H 10%; C = 10 nF 10%). The series resistance of the crystal must be below 60 . Cxtal1 = 4.7 pF 10%; Cxtal2 = 12 pF 10%). 2. Strongly depends on the external decoupling capacitor connected to Vref. 3. Use for calculation of the power-on reset set-up time the Cref value in F. 4. The audio information from the USB interface is fed directly to the ADAC. APPLICATION INFORMATION The UDA1321 is designed to be used as a self-powered device. The I2C-bus EEPROM is optional and can be used e.g. to program your own Vendor ID and Product ID. In order to help customers with defining there own configuration map, a special program called `Configuration map editor' has been developed. It is available from your local Philips Semiconductors Field Application Engineer. More information about the firmware, descriptors and configurations can be obtained from several application notes.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
USB-DAC UDA1321/N101 (FIRMWARE SW 2.1.1.7)
UDA1321
The following items are different for the UDA1321/N101 compared to the general content of this data sheet: * Volume control * Treble control * Power management. Table 10 Volume control characteristics wVOLUME B15 0 1 1 1 1 1 1 1 1 1 1 ... 1 1 1 1 1 ... 1 B14 0 1 1 1 1 1 1 1 1 1 1 ... 1 1 1 1 1 ... 0 B13 0 1 1 1 1 1 1 1 1 1 1 ... 0 0 0 0 0 ... 0 B12 0 1 1 1 1 1 1 1 1 1 1 ... 0 0 0 0 0 ... 0 B11 0 1 1 1 1 1 1 1 1 0 0 ... 0 0 0 0 0 ... 0 B10 0 1 1 1 1 0 0 0 0 1 1 ... 1 1 0 0 0 ... 0 B9 0 1 1 0 0 1 1 0 0 1 1 ... 0 0 1 1 0 ... 0 B8 0 1 0 1 0 1 0 1 0 1 0 ... 1 0 1 0 1 ... 0 VOLUME USB SIDE (dB) 0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 ... -58 -59 -60 -61 -62 ... - VOLUME USB DAC (dB) 0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 ... -58 -59 -60 - - ... -
The treble control is available for the master channel of the UDA1321. Treble can be regulated in three modes: minimum, flat and maximum mode. The preferred mode is selected via the configuration map. The corner frequency is 3000 Hz for the minimum mode and 1500 Hz for the maximum mode. The treble range is from 0 to 6 dB (discrete steps 0, 4 and 6 dB). It should be noted that the negative treble values as defined in the "USB Device Class Definition for Audio Devices" are not supported by the UDA1321; the 0 dB value is returned as 0 dB. Table 4 gives the mapping of the bTreble value upon the actual treble setting of the USB DAC.
1998 Oct 06
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
Table 11 Treble control characteristics bTREBLE B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 TREBLE USB SIDE (dB) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 ... 5.25 ... 7.25 ... 9.25 ... 31.75 6 0 6 0 6 0 6 0 6 0 4 0
UDA1321
TREBLE USB DAC (dB) minimum 0 flat 0 maximum 0
4
6 6 6 6 6
The power saving mode is not supported (no power management). The content of the four internal configuration maps is written in the `sw 2.1.1.7 configuration maps' document. This document is available at your local Philips Semiconductors Field Application Engineer.
1998 Oct 06
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
APPLICATION DIAGRAM
UDA1321
handbook, full pagewidth
C8 47 F (16 V) C14
+VA R15 1
VSSA 44 BCK digital input WS DI GP0/BCKI GP5/WSI GP1/DI 64 2 7
100 nF (63 V)
VDDA 45
+VC
P5
1 2 3 4
L9
1 2 3 4 8 7 6 5 C26 10 nF (50 V) C4 22 pF (63 V)
R9 1.5 k R14 22 R13 C5 22 pF (63 V) 22 D+ D- 17
20
C27 10 nF (50 V)
C7 10 nF (63 V)
L10 1.5 H
XTAL2
38
UDA1321H
C6 12 pF (63 V) X1 C13 4.7 pF (50 V) 48 MHz XTAL1
37
VA(ext)(1)
L15 BLM32A07 L14 BLM32A07 L16 BLM32A07 C1 100 F (16 V) C2 100 F (16 V)
+VA +VC +VD C3 100 F (16 V)
VD(ext)(2)
GND
29 VSSI C16 100 nF (63 V) C15
25 VDDI
30 VSSE C18 100 nF (63 V) C17 100 nF (63 V)
32 VDDE
L11 BLM32A07
L12 BLM32A07
(1) BLM32A07. (2) VD(ext) can be connected to 5 V max. (5 V tolerant I/O).
MGM842
100 nF (63 V)
1 R16 +VC
1 R17 +VD
Fig.11 Application diagram QFP64 (continued in Fig.12).
1998 Oct 06
36
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
UDA1321
handbook, full pagewidth
56 57 58 59 60 62 63 5 9
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ALE
D7 D6 D5 D4 D3 D2 D1 D0 LE OE
18 17 14 13 8 7 4 3 11 1
19 16 15 12
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 VCC C24 GND +VD 100 nF (50 V)
A0 A1 A2 A3 A4 A5 A6 A7 A8
10 9 8 7 6 5 4 3 25
11 12 13 15 16 17 18 19
O0 O1 O2 O3 O4 O5 O6 O7
D3 74HCT373D
9 6 5 2 20
D2 A9 24 EEPM27128
A10 A11 21 23 2 26 22 20 27 1 14 28
10 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 PSEN EA +VD R20 1 C23 100 nF (63 V) A0 A1 A2 VSS 1 2 3 4
VCC C25 GND
A12 A13 OE CE PGM VPP +VD
+VD 100 nF (50 V)
11 12 18 19 21 22 8 6
3 8 VDD PTC SCL SDA R6 10 k R7 10 k P8 1 2 1 +VD J1
R8 4.7 k 2
+VD
(internal ROM external ROM)
UDA1321H
D4 PCX8582X-2
7 6 5
4 3 42
SDA SCL VREF C22 100 nF (63 V) C10 VOUTR VOUTL C11 47 F (16 V) 47 F (16 V) C12 47 F (16 V)
SDA SCL
(I2C-bus)
46 53
audio output
14 13 10 61 55 15 49 VSSO C19 100 nF (63 V) C9 47 F (16 V) 51 VDDO 36 VSSX C21 100 nF (63 V) C28 100 nF (63 V) 39
GP4/BCKO GP3/WSO GP2/DO RTCB TC SHTCB
BCK WS DO digital output
VDDX
L13 BLM32A07
1 R18 +VA
1 R19
MGM843
+VC
(1) BLM32A07.
Fig.12 Application diagram QFP64 (continued from Fig.11).
1998 Oct 06
37
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handbook, full pagewidth
1998 Oct 06
BCK digital input L6 X4 11 22 33 44 8 7 6 5 10 nF WS DI
Philips Semiconductors
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
+3.3 V 100 F 1 1
+3.3 V 1 1 A0 A1 1 8 VDD
100 nF 100 nF
(1)
100 nF
(1)
100 nF
(1)
PTC 2 7 PCX8582X-2 A2 SCL 3 6 VSS 4 5 SDA
+3.3 V
100 nF VSSI 8 (9) GP0/BCKI GP5/WSI GP1/DI +3.3 V 1.5 k 22 D- 22 D+ 22 pF 22 pF 24 (27) 25 (29) 28 (32) VDDI 7 (8)
100 nF VSSE 9 (10) VDDE 10 (11)
100 nF VSSX 11 (13) VDDX 14 (16) (31) 27 (30) 26 (18) 15
10 k SDA SCL Vref 100 nF VOUTL 47 F 4.7 F
10 k
(I2C-bus)
(24) 21 5 (6) 6 (7) (21) 18
LEFT
38
VOUTR 47 F
RIGHT
10 nF XTAL2 10 nF 1.5 H 13 (15)
UDA1321T (UDA1321PS)
(23) 20 (22)19 (20) 17
VDDO VSSO VDDA VSSA GP4/BCKO GP3/WSO GP2/DO RTCB TC SHTCB
MGM844
100 nF
1
+3.3 V
100 nF
1
+3.3 V
12 pF 48 MHz XTAL1 4.7 pF
(19) 16
(3) 3 12 (14) (2) 2 (1) 1 (26) 23 (25) 22
BCK WS DO digital output
Preliminary specification
UDA1321
Pin numbers in parenthesis represent the UDA1321PS. (1) BLM32A07.
(4) 4
Fig.13 Application diagram SO28 and SDIP32.
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
PACKAGE OUTLINES QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
UDA1321
SOT319-2
c
y X
51 52
33 32 ZE
A
e E HE A A2 A1 (A 3) Lp bp 64 1 wM D HD ZD B vM B 19 vMA 20 detail X L
pin 1 index
wM
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1998 Oct 06
39
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
UDA1321
SO28: plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 A1 pin 1 index Lp L 1 e bp 14 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT136-1 REFERENCES IEC 075E06 JEDEC MS-013AE EIAJ EUROPEAN PROJECTION A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 18.1 17.7 0.71 0.69 E (1) 7.6 7.4 0.30 0.29 e 1.27 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.050 0.055 0.394 0.016
0.035 0.004 0.016
8o 0o
ISSUE DATE 95-01-24 97-05-22
1998 Oct 06
40
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
UDA1321
SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)
SOT232-1
D seating plane
ME
A2 A
L
A1 c Z e b 32 17 b1 wM (e 1) MH
pin 1 index E
1
16
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 29.4 28.5 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT232-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1998 Oct 06
41
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). SDIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. QFP and SO REFLOW SOLDERING Reflow soldering techniques are suitable for all QFP and SO packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body.
UDA1321
For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. WAVE SOLDERING
QFP
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners.
SO
Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end.
1998 Oct 06
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)
Method (QFP and SO)
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values REPAIRING SOLDERED JOINTS
UDA1321
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 Oct 06
43
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545102/750/04/pp44
Date of release: 1998 Oct 06
Document order number:
9397 750 04262

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